Ahmed Sam Fouad

Senior ML Optimization Engineer / Core AI

CARIAD, Volkswagen, Munich, Germany | 09/24 - Present | Full-time

• Optimized production computer vision models for real-time in-vehicle inference, analyzing end-to-end AI pipelines, identifying performance bottlenecks, and improving execution efficiency across heterogeneous compute platforms.
• Performed in-depth inference profiling and hot-path analysis using NVIDIA TensorRT and CUDA tooling, investigating execution latency, kernel performance, memory bottlenecks, and optimization opportunities in production workloads.
• Developed and optimized custom operators for Qualcomm Hexagon NPU (HTP, HVX, HMX), leveraging low-level SIMD/VLIW vectorization to achieve near-theoretical peak compute efficiency in compute-bound kernels.
• Optimized ONNX models for resource-constrained edge deployment through post-training quantization (PTQ), pruning, and graph-level optimizations; explored TVM-based kernel compilation and multi-node reduction operations on experimental Qualcomm hardware.
• Maintained and refactored heterogeneous AI inference and offloading infrastructure supporting CUDA, Qualcomm HTP, CPU, and ONNX operators, including investigations into XLA-based JIT compilation.
• Contributed to the integration and deployment of computer vision models into production vehicle platforms, collaborating with feature teams on inference performance analysis, runtime troubleshooting, and model optimization.
• Prototyped distributed multi-GPU training using NCCL collectives and MPI-based CPU–GPU offloading, reducing synchronization barriers by nearly 40%.

Senior Software Engineer / HMI Infotainment Cluster

CARIAD, Volkswagen, Munich, Germany | 03/22 - 08/24 | Full-time

• Architected and implemented robust HMI backend algorithms, optimizing HD complex maps data processing
• Implemented zero-copy inter-process communication using Iceoryx and low-latency RPC with Flatbuffers for the HMI abstraction backend module in Simulation-in-the-Loop (SiL)
• Reduced interface maintenance by 90% through automated interface generation pipeline using Jinja2 templates
• Optimized HMI backend performance, achieving 2x core kernel speedup and 30% memory footprint reduction via advanced C++ template meta-programming, enabling multi-target deployment and requiring significantly less maintenance
• Led development of HMI infotainment digital twin cluster initiative in Qt SDK
• Spearheaded dynamic ADAS HMI communication stack development, adopted across multiple projects
• Eliminated heavy and repetitive usage of interfaces adapters via lightweight proper variant interface decomposition
• Designed a unified HMI backend interface that statically carries predefined and compiled custom payloads between multiple customer functions
• Developed enabler tooling GUI apps to visually design a custom payload for the HMI interface using React SDK and React Flow
• Migrated the development environment from VM based development to local devhost inside WSL2 and docker devcontainers

Graduate Research Assistant / ExaHype2

Technische Universität München, Germany | 04/23 - 12/23 | Part-time

• Accelerated ExaHyPE Rusanov solver performance with CUDA-based Euler kernels, profiling the bandwidth bound problem, achieving near theoretical peak performance
• Improved GPU offloading efficiency for complex grid geometries using CUDA
• Achieved a 28x speedup over baseline OpenMP implementations

Software Engineer / ADAS Simulation

Altran Deutschland, Munich, Germany | 10/18 - 02/22 | Full-time

• Co-developed Linux Model Environment (LiME) server for robust ADAS sensor simulation
• Built LiME Juicer, a high-fidelity 3D environment rendering engine based on Open Simulation Interface (OSI)
• Integrated OSI, FMI, and ProtoBuff standards into LiME Juicer
• Design the multi-thread/multi-process render architecture for real-time steady 60 FPS Sensor data and point-cloud OSI payloads render engine using CUDA, OpenMP, MPI and OpenGL
• Achieved 6x rendering speedup through CUDA kernel optimization
• Developed reliable low-latency communication drivers using TCP/IP v4, SomeIP, FMU, and ZMQ

Software Engineer / Automotive Steering Development

Robert Bosch, Germany/Vietnam | 12/17 - 09/18 | Full-time

• Developed and deployed functional Auto Steering module with comprehensive SWRE requirement analysis that is ASIL-D compliant
• Implemented robust CAN and UDS protocols with 100% test coverage
• Reviewed and maintained functional safety requirements and software for ASIL-D, MISRA, and ISO26262 standards
• Developed user-friendly GUI/CLI applications using Tkinter and Qt for configuration management and for automation of repetitive tasks

Embedded Systems Engineer

Fpt Software Co./Renesas RVC, Vietnam | 07/15 - 11/17 | Full-time

• Developed lightweight Car Rear View Camera driver
• Optimized SPI and MCU drivers for iMX6, reducing latency by 10% on baremetal x86_64 Linux
• Migrated legacy modules to AUTOSAR BSW drivers

Field Maintenance Engineer

General Motors, Egypt | 02/15 - 05/15 | Full-time

• Maintained plant operations in PLC and developed efficient maintenance plans to reduce production downtime
• Proposed and implemented IP to integrate advanced sensors into production lines, improving ergonomics and safety

Surflow - Chrome Extension

Personal Project | Chrome Store

• Efficiently streamline the browsing and tab management experience
• Built with TypeScript, React, and Chrome Extension APIs

Distributed ONNX Training with NCCL

Personal Project | 09/23

• Developed a PoC for distributed training of an ONNX-based CNN model across two local GPUs using NCCL’s AllReduce and Broadcast ops
• Achieved ~1.5x speedup over single-GPU baseline by optimizing inter-GPU networking with NCCL over NVLink

TVM and XLA Optimization for TPU-Accelerated Inference proto

TUM | Advanced Computer Architecture Seminar | 02/23

• Developed a demo using TVM and XLA to compile and optimize an ONNX model for edge HW inference in runtime (Google's TPU), integrating PyTorch with XLA’s JIT compilation
• Used AutoTVM to tune convolution kernels and XLA to fuse tensor operations, reducing inference latency improving throughput by 10% compared to baseline ONNX runtime

Gem5 simulation model to evaluate Intel Skylake-based CPU

Case study

• Developed a gem5 simulation model to evaluate Intel Skylake-based CPU performance for HPC workloads
• Implemented a custom out-of-order core model in C++ within gem5’s x86 framework, simulating a 4-core Skylake processor with a 3-level cache hierarchy
• Configured gem5 to run an OpenMP-parallelized matrix multiplication benchmark and an MPI-based stencil computation workload
• Analyzed cache miss rates and branch prediction accuracy, optimizing prefetching to reduce memory latency by 12% in simulations

Master's Thesis — LLM Inference Optimization on Tenstorrent AI Accelerators

Technical University of Munich (TUM) | M.Sc. Computational Science and Engineering

• Evaluated and optimized Llama 3.1 8B and Qwen 2.5 7B inference on Tenstorrent Wormhole B0 RISC-V-based AI accelerators, focusing on memory-bandwidth-bound autoregressive decoding.
• Characterized DRAM and Network-on-Chip (NoC) performance through hardware microbenchmarking, roofline analysis, and kernel-level profiling.
• Implemented and evaluated KV cache optimizations using hardware-native BFP8/BFP4 quantization, PyramidKV, and StreamingLLM to reduce memory bandwidth requirements during long-context inference.

Guided Research

TUM | Optimizing GPU Offloading with CUDA for a Patch-based Hyperbolic Finite Volume Solver in ExaHyPE